1. Field of the Invention
The invention relates to a method of fabricating an dynamic random access memory (DRAM), and more particularly to a method of fabricating a capacitor with a higher capacitance in a DRAM, by increasing surface area of an electrode.
2. Description of the Related Art
As the function of a microprocessor becomes more and more powerful, the program and calculation of a software becomes more and more complicated, and thus, the required capacitance of a memory is larger and larger. FIG. 1 shows a circuit diagram of a conventional DRAM. A memory cell comprises a transfer transistor 10 and a storing capacitor 11. The source region of the transfer transistor 10 corresponds to a bit line 12, whereas the gate corresponds to a word line 13. The drain region of the transfer transistor 10 connects with the storing electrode 14, that is, the bottom electrode of the capacitor 11. The plate electrode 15, that is, the top electrode or the cell electrode, connects with a constant voltage source. A dielectric layer is formed between the storing electrode and the plate electrode.
The capacitor is the heart for storing input signal in a DRAM. For a large amount of charges to be stored in a capacitor, it is more frequent that an soft error is caused by noise, such as an .alpha. particle, during data access, and therefore, the refresh frequency is reduced. Several ways are available to increase the storing capacitance of a capacitor. (1) Using a dielectric layer with a higher dielectric constant, the storing charge per unit area is increased. (2) To decrease the thickness of the dielectric layer, a higher capacitance can be obtained. However, the quality of the dielectric layer restricts the thickness of the dielectric layer to a certain value. (3) By increasing the surface area of a capacitor, the amount of charges stored in a capacitor is increased. However, with increasing the surface area of a capacitor, the integration of a device is decreased.
For a conventional DRAM with a smaller amount of storing charges, a two dimensional planar type capacitor is adapted in a integrated circuit. The planar type capacitor occupies a sizeable surface area on the substrate, and therefore, not suitable for the use in a high integrated circuit. To achieve a high integration, a three dimensional structure of a capacitor, such as a stacked type or a trench type capacitor is adapted. However, as the integration becomes further higher, a pure three dimensional capacitor can not meet the requirement to be used. A method of increasing capacitance in a small area of a capacitor in a DRAM is developed.
Referring to FIG. 2a to FIG. 2b, a conventional method of fabricating a trench type capacitor in a DRAM is shown. Referring to FIG. 2a, a substrate 200 having a field oxide 201, a gate 202, an exposed source/drain regions 203, 204, 205, and a first insulation layer 206 to cover the gate 202 formed thereon is provided. A first poly-silicon layer is formed and defined to form a bit line 207 coupled with the source/drain region 204. A second insulation layer 208 is formed and patterned to cover the bit line 207 only, and expose the source/drain regions 204, 205.
Referring to FIG. 2b, a thin and doped second poly-silicon layer 209 is formed and coupled with source/drain regions 203, 205. A photo-resist layer 210 is formed on the second poly-silicon layer 209. A via 211 is formed by patterning the photo-resist layer and penetrates through the photo-resist layer 210, the second poly-silicon layer 209, and the second insulation layer 208. The via 211 is filled with an oxide layer 212. Referring to FIG. 2c, the photo-resist 210 is removed and a third poly-silicon layer 213 is formed. Referring to FIG. 2d, the third poly-silicon layer 213 on the oxide layer 212 is removed to expose the oxide layer 212. The oxide layer 212 is removed, and a storing electrode coupled with the source/drain region 204 is formed. After the formation of a dielectric layer and a fourth poly-silicon layer as a plate electrode, a capacitor is formed. The subsequent metallization and insulation protection process are then performed to complete the fabrication of a DRAM.
Referring to FIG. 3, the cross sectional view of a conventional stacked type capacitor in a DRAM is shown. A substrate 30 having a metal-oxide-semiconductor (MOS) 32 comprising a gate 33, a source/drain region 35 and a spacer is provided. On the substrate 30 with a field oxide layer 36 and a conductive layer 37 formed thereon, an insulation layer 38 is formed. A contact window is formed by etching the insulation layer 38 to exposed the drain/source region 34. A bottom electrode 39, a dielectric layer 310, and a top electrode 311 is formed on the contact window in sequence to form a stacked type capacitor 312. The dielectric layer is, for example, an oxide/nitride/oxide (ONO) layer. The bottom electrode 39 and the top electrode 311, for example, are poly-silicon. The bottom electrode has an accidented topography. After the subsequent process of metallization and insulation protection, a DRAM is fabricated.
The capacitor in a conventional DRAM adapts an accidented topography, that is, an uneven surface to obtain a higher capacitance. The disadvantage is that the degree to increase is limited. For a even higher requirement of capacitance, or a device with further smaller dimension, this kind of capacitor does not meet the requirement for application. Moreover, to fabricate a stacked type capacitor, quite a few photo-masks are used, and therefore, the process is more complex and the fabricating cost is increased.